Enabling the industry's first 64 Gbps UCIe IP following the successful registration of Alphawave Semi's Gen2 36 Gbps UCIe IP on TSMC's 3nm technology, supporting both high-throughput, low-cost organic substrate standard packaging (NYSE:) and advanced packaging technologies .
LONDON & TORONTO–( BUSINESS WIRE )– Alphawave Semi (LSE: AWE), the global leader in high-speed connectivity and computational silicon for global technology infrastructure, proudly introduces its first Universal 64 Gbps Chiplet Interconnect Express (UCIe™) Die-to-Die (D2D) IP subsystem to deliver unprecedented data rates for chip interconnection, setting a new standard For the industry's highest performing D2D communication solutions. The third generation, 64 Gbps IP subsystem builds on the successes of the latest Gen2 36 Gbps IP subsystem and the proven Gen1 24 Gbps system on silicon, and is available on 3nm technology from TSMC for both Standard and advanced packaging. The proven success of the silicon and ribbon milestones paves the way for Alphawave Semi's Gen3 UCIe™ IP subsystem offering.
Alphawave Semi is set to revolutionize connectivity with Gen3 64 Gbps UCIe IP, delivering bandwidth densities of over 20 Tb/mm, with ultra-low power and latency. This solution is highly configurable and supports multiple protocols, including AXI-4, AXI-S, CXS, CHI, and CHI-C2C to meet the increasing demands for high-performance connectivity across disaggregated systems in high-performance computing (HPC), data centers, and artificial intelligence (AI) applications.
The design is compliant with the latest UCIe™ specifications and has a scalable architecture with advanced testable features, including live health monitoring of each lane, making it a solid foundation and enabling an open and interoperable chip ecosystem.
UCIe D2D links facilitate a range of standard and emerging communication scenarios. Common uses include interconnecting compute chips for consistent, low-latency connectivity via UCIe's broadcast capabilities, as well as connecting compute to I/O chips using UCIe interfaces with PCIe, CXL, or Ethernet. Additionally, optical timers can leverage UCIe chipset architecture to create reliable, low-latency optical I/O links through optical engines, enhancing out-of-system communication. This supports the development of low-power, high-speed solutions in data centers and AI/ML systems.
For high-performance applications, creating a custom HBM base die using the latest UCIe standards is a cutting-edge approach that involves tightly integrating memory die with compute die to achieve extremely high bandwidth as well as low latency between components. This allows the die-to-die shoreline already occupied on the master die to be reused for core-to-core or core-to-I/O communications. This approach dramatically improves memory parameters in AI applications where low power and low latency are performance differentiators.
Brian Rea, Chair of the UCIe Marketing Working Group, said he was pleased to see members achieving important milestones such as cassettes, which demonstrate the growing adoption of the UCIe specifications. UCIe is a cornerstone of the chipset industry, providing a powerful solution for high-speed, low-latency interconnects. By embracing open standards, we empower industry to accelerate innovation, reduce time to market, and deliver groundbreaking technologies.
“Our success in producing 36Gbps Gen2 UCIe™ IP on 3nm technology builds on our proven, leading-edge 3nm UCIe IP technology on silicon with CoWoS packaging,” said Mohit Gupta, Senior Vice President and General Manager, Custom Silicon and Intellectual Property, Alphawave Semi. ®”. “This milestone paves the way for our third generation 64 Gbps UCIe IP, which aims to deliver high-performance, 20 Tbps/mm throughput jobs for our customers who need to maximize shoreline density to meet critical AI bandwidth needs in 2025.” .
This achievement, combined with Alphawave Semi's previous proven 3nm Gen1 UCIe IP, underscores the company's rapid progress as a leader in high-performance chip connectivity solutions with a full range of systems. Proven silicon sub-IP connectivity designed specifically for hyperscale and data infrastructure. Markets.
Learn more:
- Discover Alphawave Semi's UCIe™ IP solutions.
- Read our Recent press release about the first UCIe with industry-proven 3nm technology™ intellectual property.
- Discover our site Multi-Protocol Chipset Press Release.
- Watch the DAC 2024 video: From simulation to silicon: UCIe for Alphawave and Keysight™ ratification.
- Read our blog: Redefining XPU memory for AI data centers with custom HBM.
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About Alphawave semi
Alphawave Semi is a global leader in high-speed connectivity and computing silicon for the world's technology infrastructure. In the face of exponential data growth, Alphawave Semi meets a critical need: enabling data to travel faster, more reliably, with higher performance, and with less power. We are a vertically integrated semiconductor company, and our IP, custom silicon and connectivity products are deployed by tier-1 global customers in data centers, compute, networking, AI, 6G/5G, autonomous vehicles and storage. Founded in 2017 by an experienced technical team with a proven track record in licensing semiconductor intellectual property, our mission is to accelerate the critical data infrastructure at the heart of our digital world. To learn more about Alphawave Semi, visit: awavesemi.com.
Alphawave Semi and the Alphawave Semi logo are trademarks of Alphawave IP Group plc. All rights reserved.
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Claudia Cano Manuel
GRAND BRIDGES MARKETING LIMITED
Click on @awavesemi.com
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Source: Alphawave semi
